Exploit the flexibility of RISC-V and High-Level uArch Designs to generate cores spanning a wider design-space from a single code-base. From IoT controller to a High-performance Linux Core - All from the same code-base.

Overview

The Core Generator is an automated toolchain that allows users to configure individual hardware components of the core using Python. The generator finally emits a synthesizable instance of the core, along with other subsystem components like fabric, uncore and accelerators

Leveraging tech like RISCV- CONFIG, the user has fine grain control on several Privileged and Unprivileged architectural choices. Core Generators from InCore translate these choices to RTL.

Design Methodology

  1. Exploiting the uArch agnostic features of RISC-V, each baseline core is flavored with numerous amounts of ISA independent configurations, enabling wider design span across PPA.
  2. Our Core generators also automate generation of Docs, Physical Design collaterals, FPGA collaterals, ASIC collaterals and Software Toolchain for quick prototyping and integration.
  3. A configurable core warrants a Configurable Verification Environment and InCore also provides a python configurable parameterized test-suite to generate a comprehensive suite of tests to completely validate all micro-architectural features of a RISC-V core instance. Scalable test-harness generation capabilities to verify any core. Test parameterization and automation of test-

Example configs 

  1. RV64IMFC+Cache for Security Systems, Wearables
  2. RV32IMB+Cache for Energy Meters and Motor Controllers
  3. RV32I [Min] for Autonomous Controllers, Sensor Fusion

Key features

Flexibility at its Core

Craft a processor that fits your exact needs with our highly configurable core generator.

Parameterized Precision

Build with confidence knowing your custom core is “correct by construction” and seamlessly integrates into a variety of applications.

Seamless Integration

Build with confidence knowing your custom core seamlessly integrates into a variety of applications.

Azurite Core-hub Gen

Targeted for the deeply embedded segment

Key features:

  • An in-order 2-stage 64/32-bit processor supporting the latest subset of the ISA.
  • Single issue
  • Targets mid-range compute systems: 150-300 MHz.
  • Variants for low-power and resource constrained applications

Specifications:

  • Supports RISC-V ISA: RV[64|32]IMACUBP.
  • Supports the OpenOCD based debug environment through JTAG. Non-invasive Debug architecture and Trigger support.
  • Non-Coherent Multi-core (heterogenous) support available.
  • Support for Resumable NMIs
  • Support for Performance Counters
  • Caches: upto 32KB blocking Instruction and Data caches.
  • Simple operand Bypass.
  • Custom CSR Support with daisy chain scheme.
  • Instruction Trace support
  • PMP Support
  • Positioned against ARM’s Cortex Mx

InCore's Azurite Core Generator fuels innovation tailored to diverse applications in the deeply embeeded segments from IoT devices to mini wearables to smart cards. Azurite core-hubs are an extremely efficient implementation for very low area and power. Replace your traditional 8-bit and 32-bit applications with core-hubs from this Azurite core-generator.

IoT
Security
Motor Control
Wearables
Smart Cards
Sensor Fusion

Resources 

Calcite Core-hub Gen

Targeted toward the embedded and industrial segments

Key features:

  • An in-order 5-stage 64/32-bit processor supporting the entire stable RISC-V ISA: RV64GC [HBP*].
  • Single issue
  • Targets mid-range compute systems: 500-800MHz.
  • Supports RISC-V Linux, secure L4
  • Variants for low-power and high-performance.
  • Positioned against ARM’s Cortex A35

Specifications:

  • Supports RISC-V ISA: RV[64|32]IMAFDCSU [HBP].
  • Compatible with latest privilege spec (v1.21) of RISC-V ISA and supports the sv32/39/48/57 virtualization scheme.
  • MMU and PMP support.
  • Single and Double Precision Floating point units compliant with IEEE-754.
  • Supports the OpenOCD based debug environment through JTAG. Non-invasive Debug architecture.
  • Includes a High performance branch predictor with a Return-Address-Stack.
  • Caches: 16KB blocking pipelined Instruction and Data caches.
  • Simple Scoreboard for operand Bypass.
  • Custom CSR Support with daisy chain scheme.

InCore's Calcite Core Generator fuels innovation tailored to diverse applications in the embeeded and industrial segments from POS terminals to IP cameras. Calcite core-hubs are embedded processors providing an optimal balance of area, power and performance; capable of supporting full-featured operating systems such as Linux.

IoT
IP Camera
AR/VR
Wearables

Resources 

Dolomite core-hub Gen

Key features:

  • An in-order 7/8-stage 64/32-bit processor supporting the entire stable RISC-V ISA: RV64GC [HBP*].
  • Dual issue
  • Multiple- ALUs to reduce load-to-use latencies
  • Targets mid-range compute systems: 800MHz – 1.5GHz.
  • Supports RISC-V Linux, secure L4
  • Positioned against ARM’s Cortex A55

Specifications:

  • Supports RISC-V ISA: RV[64|32]IMAFDCSU [HBP].
  • Compatible with latest privilege spec (v1.21) of RISC-V ISA and supports the sv39/48 virtualization scheme.
  • MMU and PMP support.
  • Single and Double Precision Floating point units compliant with IEEE-754.
  • Supports the OpenOCD based debug environment through JTAG. Non-invasive Debug architecture.
  • Includes a High performance branch predictor with a Return-Address-Stack.
  • Caches: 16KB blocking pipelined Instruction and Data caches.
  • Simple Scoreboard for operand Bypass.
  • Custom CSR Support with daisy chain scheme.
  • Instruction Trace Support

InCore's Calcite Core Generator fuels innovation tailored to diverse applications in the embeeded and industrial segments from POS terminals to IP cameras. Calcite core-hubs are embedded processors providing an optimal balance of area, power and performance; capable of supporting full-featured operating systems such as Linux.

Smartphones
IP Camera
AR/VR
Wearables

Resources 

Resources

Core-generators white paper (World of customisability - customizable CPU cores and innovative processor design) by Neel, CTO
Learn More
Envision newer business models with core-generators – Deepak, CMO
Learn More
Azurite core-gen brochure 

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