RISC-V: Unveiling the Potential of Open-Source ISA

RISC-V, an open ISA based on RISC principles, originated at UC Berkeley around 2010 and was standardized in 2013. It's gaining traction as an alternative to proprietary ISAs like ARM or x86 due to its open-source nature and customizable features. Its configurability and modularity have fueled its rapid adoption, allowing vendors to tailor processors for various workloads. InCore leverages this modularity to design highly configurable processors, offering tailored instances for specific RISC-V subsets. With its open-source, scalable architecture, RISC-V provides significant advantages for developers, making it an exciting technology for the future. Learn more at riscv.org.

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Core Generators: Streamlining Custom Processor Design

What makes us different: Automated design flow

SaaS agility to hardware

By leveraging Continuous Integration/Continuous Deployment (CI/CD) methodologies, hardware engineering endeavors are undergoing a transformative shift akin to the agility observed in Software as a Service (SaaS) development. CI/CD facilitates the seamless integration of iterative changes and automated testing into the hardware development pipeline, enabling rapid prototyping, enhanced collaboration, and efficient scaling. This approach streamlines the traditionally cumbersome hardware development process, reducing time-to-market and fostering innovation by enabling engineers to swiftly adapt to evolving requirements and feedback. As a result, the integration of CI/CD principles into hardware engineering not only enhances productivity but also ensures the delivery of high-quality, reliable products at scale, mirroring the agile practices prevalent in SaaS development.

Parametrized Libraries

Advanced HDL represents a pioneering approach within the industry, distinguished by its unparalleled methodology that prioritizes correctness through construction, resulting in a significant reduction in bugs. This innovative methodology not only sets new standards but also ensures higher efficiency and reliability in hardware design. By embracing correct-by-construction principles, it also empowers engineers to develop complex designs with greater confidence, ultimately driving forward the evolution of hardware development practices.

Automated verification

InCore innovates verification processes by leveraging verification generators, automating complex procedures and minimizing errors. Automated test generation ensures thorough coverage of corner cases, guaranteeing core reliability across diverse conditions. Additionally, InCore integrates continuous integration, regression testing, and standardized test suites to uphold rigorous verification standards throughout the design process, encompassing ISA compliance, uArch compliance, and random testing.

YAML to all things silicon

Custom software

InCore pioneers custom software development by automating application stack generation from user specifications. Our streamlined approach simplifies user input, automates stack creation, and ensures seamless alignment with user needs. This innovative process accelerates development cycles, reduces costs, and empowers users to shape their software solutions effortlessly.

Pre-defined templates

InCore offers pre-defined SoC templates, streamlining custom hardware development. Understanding market needs is key, and our platform provides a robust starting point for hardware projects. Leveraging our templates, clients swiftly align their solutions with market demands, saving time and resources. Our programmatically generated custom hardware ensures precise configurations tailored to diverse industry requirements, empowering clients to innovate confidently.

FPGA flows

InCore streamlines FPGA flows, enabling instant FPGA prototyping on standard platforms like Xilinx. This approach ensures prototyping, firmware, and software teams are operational from day one. By providing out-of-the-box FPGA prototyping, we foster seamless collaboration and rapid iteration, enhancing productivity and innovation for successful project outcomes.

ASIC flows

InCore accelerates ASIC flows, providing PPA (Power, Performance, Area) landing zones as soon as the design is released. This swift access empowers teams to optimize key metrics early in the development process, ensuring efficient resource allocation and timely decision-making. By obtaining PPA landing zones promptly, we streamline the ASIC design journey, enhancing productivity and enabling faster time-to-market for innovative solutions.

Doc Generator: Streamlining Documentation for Core Instances

When working with RISC-V core generators, precision in documentation for each generated processor core instance is paramount. Our Doc Generator complements the core generator, ensuring precise alignment between documentation and the unique characteristics of each instance created. By automating the extraction of pertinent details from the core generator’s output—including configuration specifics, architecture, and features—the Doc Generator swiftly compiles a comprehensive document. This serves as an invaluable reference for engineers, developers, and stakeholders alike, streamlining the development process with clarity and efficiency.